The inventors of the present invention proposed an inverted amplifying circuit in Japanese Patent Laid-Open Publication No.7-94957 that used analog voltages to prevent unstable oscillation during computation and guarantee linearity characteristics.
FIG. 5 shows one of the circuits proposed in that reference. CMOS inverters I1, I2 and I3 in an odd number of stages are connected in series, and the output of last-stage CMOS inverter I3 is inputted to CMOS inverter I1 through feedback capacitance CF. In a circuit so structured, regardless of the load at any of the stages following I3, a voltage Vout equal to the inversion of input voltage Vin inputted to I1 is generated by the high gain of each CMOS inverter as an output of I3 with accuracy.
In the circuit in FIG. 5, a balancing resistance containing a pair of resistances RE1 and RE2 is connected to the output of CMOS inverter I2 at the stage immediately preceding the last one. RE1 and RE2 are connected to high-potential supply voltage Vdd and low-potential supply voltage Vss, respectively. Resistances RE1 and RE2 decrease the open gain of I2 and limit the gain of the entire inverted amplifying circuit.
The output of the last-stage CMOS inverter I3 is grounded through the low-pass capacitance CG. This inverted amplifying circuit has a decreased gain in the high-frequency area and an increased phase margin.
Phase margin and gain margin can be obtained as stated above, and oscillation can be prevented up to within the high-frequency area.